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							SERVICE
MANUAL
UHF FM TRANSCEIVER 
LPD FM TRANSCEIVER  
						

							INTRODUCTION
DANGER
ORDERING  PARTS
REPAIR  NOTES
This service manual describes the latest service information
for the  at the time of publication.
NEVERconnect the transceiver to an AC outlet or to a DC
power supply that uses more than 5 V. Such a connection
could cause a fire hazard and/or electric.
DO NOTexpose the transceiver to rain, snow or any liquids.
DO NOTreverse the polarities of the power supply when
connecting the transceiver.
DO NOTapply an RF signal of more than 20 dBm (100mW)
to the antenna connector. This could damage the trans-
ceivers front end.
Be sure to include the following four points when ordering
replacement parts:
1.  10-digit order numbers
2.  Component part number and name
3.  Equipment model name and unit name
4.  Quantity required

0910049951 PCB B-5109B IC-4008A MAIN UNIT 5 pieces
8810009780 Screw PH BO M2x6 ZK IC-4008A Chassis 10 pieces
Addresses are provided on the inside back cover for your
convenience.
1. Make sure a problem is internal before disassembling  the transceiver.
2.DO NOTopen the transceiver until the transceiver is disconnected from its power source.
3.DO NOTforce any of the variable components. Turn them slowly and smoothly.
4.DO NOTshort any circuits or electronic parts. An insulated turning tool MUSTbe used for all adjustments.
5.DO NOTkeep power ON for a long time when the transceiver is defective.
6.DO NOTtransmit power into a signal generator or a sweep generator.
7.ALWAYSconnect a 30 dB to 40 dB attenuator between the transceiver and a deviation meter or spectrum analyzer when
using such test equipment.
8.READthe instructions of test equipment thoroughly before connecting equipment to the transceiver.
To upgrade quality, all electrical or mechanical parts and
internal circuits are subject to change without notice or oblig-
ation.
MODEL
VERSION
Italy
C.S.AmericaSYMBOL
ITA
ITA-1
CSA
CSA-1BODY COLOR
BLACK
YELLOW
BLACK
YELLOW IC-4008A
IC-4008MK 
						

							TABLE OF CONTENTS
SECTION 1 SPECIFICATIONS
SECTION 2 INSIDE VIEWS
SECTION 3 DISASEMBLY INSTRUCTION
SECTION 4 CIRCUIT DESCRIPTION
4-1 RECEIVER CIRCUITS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
4-2 TRANSMITER CIRCUITS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
4-3 PLL CIRCUITS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
4-4 POWER SUPPLY CIRCUITS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
4-5 PORT ALLOCATIONS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
SECTION 5 ADJUSTMENT PROCEDURES
5-1 PREPARATION  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
5-2 ADJUSTMENT  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2 
SECTION 6 PARTS LIST
SECTION 7 MECHANICAL PARTS AND DISASSEMBLY
7-1 CABINET PARTS  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1
7-2 ACCESSORIES  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1 
SECTION 8 SEMI-CONDUCTOR INFORMATION
SECTION 9 BOARD LAYOUTS
9-1 MAIN UNIT  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1
9-2 RF UNIT  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-5
SECTION 10 BLOCK DIAGRAM
SECTION 11 VOLTAGE DIAGRAM
11-1 MAIN UNIT  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1
11-2 RF UNIT  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-2 
						

							SECTION 1 SPECIFICATIONS
1 - 1
All stated specifications are subject to change without notice or obligation.Number of channels
Type of emission
Frequency stability
Frequency resolution
Power supply requirements
(negative ground)
Current drain
Operating temperature range
Number of CTCSS frequency
Dimensions 
(proj. not included)
Weight (included 3 cells)
Output power
Modulation system
Max. freqequency deviation
Spurious emissions
Adjacent channel power
External mic.connector
Receiving system
Intermediate frequency
Sensitivity (12 dB SINAD)
Adjacent channel selectivity
Spurious response
Intermoduration
Audio output power
External SP connector
[ITA], [ITA-1] [CSA], [CSA-1]
RECEIVER TRANSMITTER GENERAL
69 channel (simplex; 433.075–434.775)
16K0F3E
±2500 Hz (±5.7 ppm)
25 kHz
3 
´AA(R6) dry, alkaline;or optional BP-202
less than 140 mA less than 500 mA
–10˚C to +55˚C (–14˚F to +122˚F)
38 (67.0–250.3 Hz)
55.5(W)
´102.5(H) ´26.5(D) mm
23⁄16(W)´41⁄32(H) ´11⁄32(D) inch
180 g; 7.8 oz
10 mW 500 mW
Variable reactance frequency modulation
±5.0 kHz
0.25 µW–40 dB
50 µW
more than 47 dB
3-conductor 2.5(d) mm/2.2 k½
Double conversion superheterodyne
1st: 21.7 MHz
2nd: 450 kHz
0.2 µV ;–14 dBµ
more than 40 dB
more than 40 dB
more than 40 dB
100 mW at 10% distortion with an 8 ½load
2-conductor 3.5 (d) mm (
1⁄8)/8 ½ 
						

							CHANNEL FREQUENCY LIST
CTCSS FREQUENCY LIST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23433.0750
433.1000
433.1250
433.1500
433.1750
433.2000
433.2250
433.2500
433.2750
433.3000
433.3250
433.3500
433.3750
433.4000
433.4250
433.4500
433.4750
433.5000
433.5250
433.5500
433.5750
433.6000
433.625024
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46433.6500
433.6750
433.7000
433.7250
433.7500
433.7750
433.8000
433.8250
433.8500
433.8750
433.9000
433.9250
433.9500
433.9750
434.0000
434.0250
434.0500
434.0750
434.1000
434.1250
434.1500
434.1750
434.2000 Channel No. Frequency (MHz) Channel No. Frequency (MHz) Channel No. Frequency (MHz)
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69434.2250
434.2500
434.2750
434.3000
434.3250
434.3500
434.3750
434.4000
434.4250
434.4500
434.4750
434.5000
434.5250
434.5500
434.5750
434.6000
434.6250
434.6500
434.6750
434.7000
434.7250
434.7500
434.7750
1
2
3
4
5
6
7
8
9
10
11
12
1367.0
71.9
74.4
77.0
79.7
82.5
85.4
88.5
91.5
94.8
97.4
100.0
103.514
15
16
17
18
19
20
21
22
23
24
25
26107.2
110.9
114.8
118.8
123.0
127.3
131.8
136.5
141.3
146.2
151.4
156.7
162.2 Channel No. Frequency (Hz) Channel No. Frequency (Hz) Channel No. Frequency (Hz)
27
28
29
30
31
32
33
34
35
36
37
38
---167.9
173.8
179.9
186.2
192.8
203.5
210.7
218.1
225.7
233.6
241.8
250.3
OFF
1 - 2 
						

							SECTION 2 INSIDE VIEWS
2 - 1
•MAIN UNIT
•RF UNIT
T+3 Regurator
(Q28: 2SB798)
+3 Regurator
(IC6: S-81230SG)
R+3 Regurator
(Q18: 2SA1586)
CPU
(IC1: µPD753036GK) Audio amplifier
(IC9: NJM2070M)
EEPROM
(IC3: X24C01AS)
TOP VEIW BOTTOM VEIW
1st mixer
(Q2: 2SC4226)
PLL IC
(IC1: TB31202FN)
2nd IF filter
(Fl3: CFWM450E) 1st IF amplifier
(Q1: 2SC4215) FM IF IC
(IC2: TA31136FN)
Reference oscilletor
(X1: CR-633 21.25 MHz)
VCO circuitRF amplifier 
(Q3: 2SC5194)
1st IF filter
(Fl2: FL-298)
TOP VIEW BOTTOM VIEW 
						

							SECTION 3 DISASEMBLY INSTRUCTIONS
3 - 1
AB
B
MAIN unit RF unit
ECD
F
H
G
•REMOVING THE REAR PANEL
Unscrew 1 screw , and 4 screws .
Remove the rear panel in the direction of the arrow.
•REMOVING THE RF UNIT
Remove 1 knob,  , and unscrew 1 nut, .
Unsolder 1 point, , and  then remove the RF unit.
•REMOVING THE MAIN UNIT
Unscrew 2 screws, .
Remove the PTT rubber, .
Unsolder 2 points, , and remove the MAIN unit. 
						

							4 - 1
SECTION 4 CIRCUIT DESCRIPTION
4-1 RECEIVER CIRCUITS
4-1-1 ANTENNA SWITCHING CIRCUIT (RF UNIT)
Received signals from the antenna connector are passed
through the low-pass filter (L5, L6, C8–C12). The filtered sig-
nals are applied to the 
l⁄4type antenna switching circuit (D7,
D101, D102, L4, L206, C209, C210).
The antenna switching circuit functions as a low-pass filter
while receiving. However, its impedance becomes very high
while D101 and D102 are turned ON (while transmitting).
Thus transmit signals are blocked from entering the receiver
circuits. The passed signals are then applied to the RF ampli-
fier circuit.
4-1-2 RF CIRCUIT (RF UNIT)
The RF circuit amplifies signals within the range of frequen-
cy coverage and filters out-of-band signals.
The signals from the antenna switching circuit are amplified
at the RF amplifier (Q3) and passed through the bandpass fil-
ter (FI1) to suppress out-of-band signals. The filtered signals
are applied to the 1st mixer circuit (Q2). 
4-1-3 1st MIXER AND 1st IF CIRCUITS (RF UNIT)
The 1st mixer circuit converts the received signals to a fixed
frequency of the 1st IF signal with a PLL output frequency. By
changing the PLL frequency, only desired signals will be
passed through a crystal filter at the next stage of the 1st
mixer.
The signals from the bandpass filter are mixed at the 1st
mixer circuit (Q2) with a 1st LO signal coming from the VCO
circuit to produce a 21.7 MHz 1st IF signal.The 1st IF signal
is applied to a crystal filter (FI2) to suppress out-of-band sig-
nals. The filtered 1st IF signal is applied to the IF amplifier
(Q1), then applied to the 2nd mixer circuit (IC2, pin 16).
4-1-4 2nd MIXER AND DEMODULATOR CIRCUITS
(RF UNIT)
The 2nd mixer circuit converts the 1st IF signal to a 2nd IF
signal. A double conversion superheterodyne system (which
converts receive signals twice) improves the image rejection
ratio and obtains stable receiver gain.
The 1st IF signal from the IF amplifier (Q1) is applied to the
2nd mixer section in the FM IF IC (IC2, pin 16), and is mixed
with the 2nd LO signal to be converted into a 450 kHz 2nd IF
signal.
The FM IF IC contains a 2nd mixer, quadrature detector,
noise amplifier and a limiter amplifier, etc. The PLL reference
oscillator (X1) is used for the 2nd LO signal via the PLL IC
(IC1, pins 11, 9), and is applied to pin 1 of the FM IF IC (IC2).
The mixed 2nd IF signal is output from pin 3 and passed
through the ceramic bandpass filter (FI3) to remove unwant-
ed heterodyne frequencies. It is then amplified at the limiter
amplifier section (IC2, pin 5) and applied to the quadrature
detector section (IC2, pins 10, 11) to demodulate the 2nd IF
signal into AF signals.
4-1-5 AF CIRCUIT (RF AND MAIN UNITS)
AF signals from the FM IF IC (RF unit; IC2, pin 9) are passed
through the high-pass filter (RF unit; Q15, Q16) to remove
CTCSS signals then applied to the MAIN unit via J2 pin 10 as
the “VOL” signal.
The “VOL” signal (AF signals) from the RF unit is applied to
the [VOL] control (MAIN unit; R58) to control the audio level
via the volume mute switch (Q23). The level controlled AF
signals are applied to the AF power amplifier (IC9, pin 2) to
drive an internal speaker (SP1) via the [SP] jack (J1).
• 2nd IF AND DEMODULATOR CIRCUITS
Mixer
16 Limiter
amp.2nd IF filter
450 kHz
PLL IC
IC1
X1
21.25 MHz
X2(21.25 MHz)
RSSI
IC2 TA31136FN14
1st IF (21.7 MHz)
from Q1
SQL signal to the CPU pin 59 11 10 987 5 3
AF signal AF
R+319
11
Active
filter
FI3
Noise
detector
FM
detector
C74 C75
C76
C67C77
C78 R51
R52
R53
R57 R58 
						

							4 - 2
• PLL circuit
Shift register
PrescalerPhase
detector
Loop
filter
Programmable
counter
Programmable
dividerX1
21.25 MHzto the FM IF IC 
(IC2, pin 1)
VCOBuffer
Q7
6
7
8
STB IC1 (PLL IC)
CK
DATAto transmitter circuit
to 1st mixer circuit D2
D1
9
11 1416
Q6, D4, D5
4-1-6 SQUELCH CIRCUIT (RF AND MAIN UNITS)
(1) NOISE SQUELCH
The noise squelch circuit cuts out AF signals when no RF sig-
nals are received. By detecting noise components in the AF
signals, the squelch circuit switches the AF mute switch.
A portion of the AF signals from the FM IF IC (RF unit; IC2,
pin 9) are  applied to the active filter section (RF unit; IC2, pin
8). The active filter section amplifies and filters noise compo-
nents. The filtered signals are applied to the noise detector
section and output from pin 14 as the “SQL” signal.
The “SQL” signal from IC2 (pin 14) passes through J2 pin 9,
and is then applied to the CPU (MAIN unit; IC1, pin 59). The
CPU analyzes the noise condition and outputs the “RMUT”
and “AFON” signals to toggle the volume mute (MAIN unit;
Q23) and AF mute (MAIN unit; Q5, Q10, Q11) switches.
(2) TONE SQUELCH
The tone squelch circuit detects AF signals and opens the
squelch only when receiving a signal containing a matching
subaudible tone (CTCSS). When tone squelch is in use, and
a signal with a mismatched or no subaudible tone is
received, the tone squelch circuit mutes the AF signals even
when noise squelch is open.
A portion of the AF signals from the FM IF IC (RF unit; IC2,
pin 9) passes through the tone low-pass filter (MAIN unit; Q7,
Q12) to remove AF (voice) signals and is applied to the
CTCSS decoder inside the CPU (MAIN unit; IC1, pin 58) via
the “CTCIN” line to control the volume mute and AF mute
switches.
4-2 TRANSMITTER CIRCUITS
4-2-1 MICROPHONE AMPLIFIER CIRCUIT
(MAIN UNIT)
AF signals from the internal/external microphone are applied
to the microphone amplifier circuit (IC2b) via the microphone
switch (Q6). The amplified signals are passed through the
low-pass filter (IC2a) and applied to the modulation circuit in
the RF unit via J4 pin 5 as the MOD signal.
4-2-2 MODULATION CIRCUIT (RF UNIT)
The filtered audio signals from J4, pin 5 (On the MAIN unit)
are passed through the deviation adjustment pot (R50) then
applied to the modulation circuit (D4, D5) to modulate trans-
mit signals at the VCO circuit (Q6).
The modulated signal is applied to the drive amplifier circuit.
4-2-3 DRIVE/POWER AMPLIFIER CIRCUITS
(RF UNIT)
The amplifier circuit amplifies the VCO oscillating signal to
the output power level.
The amplified transmit signal is passed through the antenna
switching circuit (D6) and low-pass filter, and is then applied
to the antenna.
The modulated transmit signal is amplified at the pre-drive
and drive amplifiers (Q8, Q201) after being amplified at the
buffer amplifier (Q7). The amplified signal is power amplified
at the power amplifier (Q202) to obtain 500 mW or
(IC–4008A) 10 mW (IC–4008MK2) of RF power.
The power amplified signal is then applied to the antenna via
the low-pass filter circuits.
4-3 PLL CIRCUITS (RF UNIT)
A PLL circuit provides stable oscillation of the transmit fre-
quency and receive 1st LO frequency. The PLL output com-
pares the phase of the divided VCO frequency to the refer-
ence frequency. The PLL output frequency is controlled by
the divided ratio (N-data) of a programmable divider.
The PLL circuit consists of the VCO circuit (Q6, D4, D5). An
oscillated signal from the VCO passes through the buffer
amplifier (Q7) is applied to the PLL IC (IC1, pin16) and is
prescaled in the PLL IC based on the divided ratio (N-data).
The reference signal is generated at the reference oscillator
(X1) and is also applied to the PLL IC. The PLL IC detects the
out-of-step phase using the reference frequency and outputs
it from pin 14. The output signal is passed through the loop
filter (R45, C68) and is then applied to the VCO circuit as the
lock voltage.
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency. 
						

							4 - 3
LINE
BATT
3V
+3V
R+3
T+3DESCRIPTION
The voltage from the connected battery pack.
Common 3 V converted from the BATT line at
the 3V regulator circuit (IC6). The circuit outputs
the voltage regardless of the power ON/OFF
condition.
Common 3 V converted from the BATT line at
the +3V regulator circuit (Q25, D4).
Receive 3 V cotrolled by the R+3 regulator circuit
(Q18) using the “RXV” signal from CPU (IC1).
Transmit 3 V converted from the BATT line at the
T+3 regulator circuit (Q27, Q28, D5, etc.) using
the “TXV” signal coming from CPU (IC1).Outputs data signals to the PLL IC (RF
unit; IC1).
Outputs strobe signals for the PLL IC
(RF unit; IC1).
Outputs control signal for the +3V reg-
ulator circuit (MAIN unit; Q25, D4).
Output port for the CTCSS signals.
Outputs control signal for the MIC
amplifier (IC2).
Low : While microphone amplifier is
ON.
Input port for the CTCSS decode sig-
nals.
Input port for squelch level signal.
Input ports for the control signal from
the external remote microphone.
Input port form the connected battery
pack for low battery indication.
Input port for the RSSI signal from the
FM IF IC (RF unit; IC2) to detect receiv-
ing signal strength level.
Outputs clock signal to the EEPROM
(IC3).
Outputs data signals to the EEPROM
(IC3).
Output port for power save function,
applied to VCO regurator circuit (RF
unit; Q13, Q14, D8, D9).
Outputs the R+3 regulator control sig-
nal (Q18).
Outputs the T+3 regulator control sig-
nal (Q27, Q28, D5, etc.).
Outputs control signal for LCD back-
light.
Low : While LCD backlight is ON.
Outputs internal microphone control
signal.
High : While internal PTT switch is
pushed.
Outputs MIC mute signal for RING
function.
High : While RING signals are out-
put, etc.51
52
53
54–56
57
58
59
60
61
62
73
74
75
76
77
78
79
80PLLDA
PLLST
POWER
CTCO0–
CTCO2
TXMOD
CTCIN
SQLIN
REMIN
BATIN
SENIN
EEPCK
EEPDA
PSC
RXV
TXV
LAMPC
MICSW
MMUTE
Pin Port
Description
number name
Input port for the PTT switch from the
external mic jack (MAIN unit; J1).
Low : External PTT switch is ON.
Input port for the internal PTT switch.
Low : While PTT switch is pushed.
Input port for the [DOWN] switch.
Input port for the [UP] switch.
Input port for the [MODE] switch.
Input port for the POWER switch.
Low : While POWER switch is
pushed.
Input port for PLL unlock signal from
the PLL IC (RF unit; IC1).
Low : During unlock.
Outputs beep audio signal.
Outputs volume mute switch (Q23)
control signal.
High : While squelched
Outputs control signal for the AF ampli-
fier regulator circuit (Q5, Q10, Q11).
High: When squelch is open.
Outputs clock signal to the PLL IC (RF
unit; IC1).
31
34
35
36
37
38
45
46
48
49
50PTT2
PTT1
DOWN
UP
MODE
POWSW
UNLK
BEEP
RMUTE
AFON
PLLCK
Pin Port
Description
number name
4-4 POWER SUPPLY CIRCUITS
VOLTAGE LINE
4-5 PORT ALLOCATIONS
4-5-1 CPU (MAIN unit; IC1)